ConSol Partners Design for Test Implementation Engineer in Sweden

Design for Test Implementation Engineer

Toulouse, France

6 month contract


The Company

A leading semiconductor company

The Role

  • Design For Test implementation with JTAG in an integrated circuit
  • Verification of the integrated circuit with the UVM methodology
  • Application of Power Management
  • Testability of integrated circuits
  • Description of the modules to be realized in Verilog and / or SystemVerilog
  • Content of state machine modules, sequencers, communication interfaces
  • Checking these modules in unit tests
  • Construction of the logic block global verification plan
  • Participation in the implementation of the audit plan
  • Verification methodology with UVM

The Individual

  • RTL for DFT
  • SystemVerilog
  • EManager / ePlanner of Cadence
  • UVM
  • JTAG
  • Experienced profile, autonomy, mixed signal DFT, UVM

Salary: €40 - €50 per hour

Consultant: James Witting